1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a vertical device and method for conserving layout area on semiconductor chips.
2. Description of the Related Art
In the semiconductor industry, it is advantageous to reduce the size and increase component density on chips. Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device. With device sizes approaching less than 0.2 microns, the decrease in the horizontal dimensions of semiconductor devices has created problems in the operational characteristics of the devices.
To accommodate the conflicting trends of reduced size and increased component density, a need exists for a vertical device which reduces the amount of area occupied of the horizontal plane of the semiconductor device. Such a device would alleviate the conflicting trends. A further need exists for an arrangement of cells in a semiconductor device layout such that an increased density of cells is provided.
A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline.
In alternate embodiments of the semiconductor device, a contact may be included for electrically connecting the bitline to the transistor. The contact may electrically connect to the transistor at a contact area and the contact area may include one of a silicide and a salicide. A buried strap may be included for accessing the storage node by the transistor wherein the buried strap is oriented substantially perpendicular to the wordline or the buried strap is oriented substantially parallel to the wordline. The wordline may further include a center region with increased conductivity relative to an outer region of the wordline. An active area may be included adjacent to the wordline for conducting between the bitline and the storage node. The active area may be utilized by at least one transistor.
In a memory cell array for a DRAM chip, each memory cell includes a vertically disposed transistor having an active area for accessing a storage node within a trench of each memory cell. A contact couples the transistor to a bitline wherein the trench, the active area and the contact have approximately same shapes for improving processing of the DRAM chip.
In alternate embodiments, the memory cells are preferably arranged in a hexagonal pattern. Bitlines may be arranged in a zig-zag pattern, arranged in a diagonal pattern or arranged perpendicularly relative to wordlines. Each memory cell may have a cell area of about 4F2 where F is a minimum feature size of the DRAM chip.
A method of fabricating a semiconductor chip having vertically orientated transistors includes the steps of providing a substrate having trenches formed therein and a storage node disposed within each trench, forming a wordline within the substrate such that a vertical side of the wordline is coupled to a portion of the substrate and electrically coupling the portion of the substrate to the storage node and to a bitline such that current is permitted to flow between the storage node and the bitline when the wordline is activated.
In alternate methods, the step of forming a wordline may include the step of forming a center portion of the wordline with a higher conductivity than an outer portion of the wordline. The step of electrically coupling may include doping the portion of the substrate. The step of doping may be performed by ion implantation or out diffusion from a doped area, e.g., from the storage node by tempering. The step of depositing a gate oxide on the portion of the substrate may be included. The step of electrically coupling the portion of the substrate to the storage node and to a bitline may include the step of forming a contact to connect the portion of the substrate to the bitline. The step of forming the contact to connect the portion of the substrate to the bitline may include providing one of a silicide and salicide between the contact and the portion of the substrate to improve conductivity. The portion of the substrate may include an active area and further comprise the step of forming the transistors to share the active area.
Another method of fabricating a semiconductor chip having trenches, vertically disposed active areas and bitline contacts includes the steps of providing a same shape for the trenches, the active areas and the bitline contacts and forming the trenches, the active areas and the bitline contacts using a same lithographic mask for the trenches, the active areas and the bitline contacts. Alternately, the method includes circular shapes. The step of forming may includes forming the trenches, the active areas and the bitline contacts using a same lithographic mask
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.